Cell-Based Multilevel Carry-Increment Adders with Minimal AT- and PT-Products

Carry-select addition techniques imply the computation of double sum and carry bits with subsequent selection of the correct values, resulting in significant area overheads. This overhead increases massively when the selection scheme is applied to multiple levels in order to further reduce computation time. A recently proposed reduced-area scheme for carry-select adders lowers this overhead by computing the carry and sum bits for a block-carry-in value of 0 only and by incrementing them afterwards depending on the final block-carry-in. The resulting carry-increment adder cuts circuit size down by 23% with no change in performance. This paper extends this increment scheme hierarchically to build multilevel carry-increment adders. It is shown that such adders are considerably faster while maintaining the same area complexity. The implemented 2-level carry-increment adder has roughly the same size as the 1-level version, but is up to 29% faster. For large word lengths (up to 128 bits), its area-delay product as well as its power-delay product is the smallest of all known adder architectures for cell-based design technologies. Comparisons are carried out on the basis of unit gate-delay and gate-count models as well as CMOS standard-cell implementations.